RTL Design of AXI4 Bus Protocol followed by AXI4-Lite Bus Protocol and Handshaking Communication Principle
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Apr 7, 2024 - Verilog
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bus-protocol
Here are 6 public repositories matching this topic...
EzBus is a true peer-to-peer token-bus protocol library intended to work on the RS-485 physical layer. Designed to run on resource constrained micro-controllers.
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Mar 12, 2021 - C
Este repositório contém os códigos, parâmetros e resultados de um ensaio de emulação de turbina eólica de eixo horizontal. O sistema utiliza um motor elétrico para mimetizar o comportamento dinâmico de uma turbina real sob perfis de vento variáveis.
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May 14, 2026 - Python
APB-controlled UART IP with memory-mapped registers, designed in Verilog and verified using simulation.
simulation verilog uart hardware-designs icarus-verilog gtkwave digital-design apb ip-core rtl-design bus-protocol
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Jan 25, 2026 - Verilog
Reverse-engineered Fujitsu FGL Type A wired bus protocol — for older Fujitsu/General air conditioners (2000-2010 era), wired remotes (EZ-0001HSEFR and similar). Full spec + Python tools.
home-automation iot esp32 reverse-engineering smart-home general hvac sigrok homeassistant loxone fujitsu air-conditioner bus-protocol protocol-spec fgl-bus
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May 10, 2026 - Python
🔌 Implement memory-mapped UART communication with an APB interface in Verilog, enabling efficient serial data transfer and modular design verification.
simulation verilog uart hardware-designs icarus-verilog gtkwave digital-design apb ip-core rtl-design bus-protocol
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May 15, 2026 - Java
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