WORKAROUND: Disable L0s to fix wlan functionality#506
WORKAROUND: Disable L0s to fix wlan functionality#506krishnachaitanya-linux wants to merge 2 commits intoqualcomm-linux:qcom-6.18.yfrom
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@krishnachaitanya-linux Why are you reverting the MSI capability change also? I understand that some hardware issue got unmasked by that change, but for that you added the WA in board dts already. Is that not enough? |
@Mani-Sadhasivam Krishna is reverting the old workaround which is the revert of MSI capability change, i.e. it's a revert of revert. |
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@krishnachaitanya-linux As this seems to be an issue with SoCs rather than boards. I wonder whether we should apply the change below instead. The commit log needs to be updated though. https://lore.kernel.org/all/20260419093934.1223027-1-shengchao.guo@oss.qualcomm.com/ |
Ack, I will update the PR now. |
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PCIe errors are resolved for now by disabling L0s for now.
So, add the change back.
Please also give a reference to the commit that addresses the earlier issue.
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@krishnachaitanya-linux You need to update the commit message of the patch from Shawn as per the comments given. Even though this is a temp WA, we should use accurate commit message. |
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This is needed for RC3 release, with out this the switch functionality is broken. In cascade switch which is enabled in this release we are seeing issues with smmu, we found that issue is due to msi capability in root complex(this is not supported in hw when synopsys SPI's are used). so we tried to backport upstream change which disables msi capability. This change is actual uncovered AER issue which is not seen till now in other targets(rb4 & rb8) very late. so we raised this PR very late to have rc3 release. |
ack |
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Ack updated it. |
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Revert "Revert "FROMLIST: PCI: dwc: Remove MSI/MSIX capability if iMSI-RX is used as MSI controller""
see if following looks better:
Revert "Revert "FROMLIST: PCI: dwc: Remove MSI/MSIX capability if iMSI-RX is used as MSI controller""
Commit bf62c12 ("Revert "FROMLIST: PCI: dwc: Remove MSI/MSIX capability if
iMSI-RX is used as MSI controller"") was applied due to excessive AER
logging and functional breakage after INTx fallback.
The AER issue is now mitigated by disabling L0s, so restore the original
behavior and remove MSI/MSI-X capabilities from Root Ports using iMSI-RX.
This reverts commit bf62c12 ("Revert "FROMLIST: PCI: dwc: Remove MSI/MSIX
capability if iMSI-RX is used as MSI controller"").
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
FROMLIST: PCI: qcom: Disable ASPM L0s for SA8775P
Missed Link: in this commit log
…I-RX is used as MSI controller"" Commit bf62c12 ("Revert "FROMLIST: PCI: dwc: Remove MSI/MSIX capability if iMSI-RX is used as MSI controller"") was applied due to excessive AER logging and functional breakage after INTx fallback. The AER issue is now mitigated by disabling L0s, so restore the original behavior and remove MSI/MSI-X capabilities from Root Ports using iMSI-RX. This reverts commit bf62c12 ("Revert "FROMLIST: PCI: dwc: Remove MSI/MSIX capability if iMSI-RX is used as MSI controller""). Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Commit f5cd8a9 ("PCI: dwc: Remove MSI/MSIX capability for Root Port if iMSI-RX is used as MSI controller") removed MSI/MSI-X capabilities from the Root Port on platforms using iMSI-RX (including SA8775P, which has no msi-parent/msi-map in DT). This causes PME and AER service drivers to fall back from MSI to INTx. There are lot of AER's seen after this change, the reason for this AER's can be board specific, and recently discovered refgen voting required by phy driver. [ 13.069528] pcieport 0000:00:00.0: PME: Signaling with IRQ 332 [ 13.082436] pcieport 0000:00:00.0: AER: enabled with IRQ 332 [ 13.082447] pcieport 0000:00:00.0: AER: Correctable error message received from 0000:01:00.0 [ 13.101347] pci 0000:01:00.0: PCIe Bus Error: severity=Correctable, type=Data Link Layer, (Transmitter ID) [ 13.111281] pci 0000:01:00.0: device [17cb:1103] error status/mask=00001000/0000e000 [ 13.111284] pci 0000:01:00.0: [12] Timeout [ 13.111313] pcieport 0000:00:00.0: AER: Multiple Correctable error message received from 0000:01:00.0 [ 13.130512] pcieport 0000:00:00.0: PCIe Bus Error: severity=Correctable, type=Data Link Layer, (Transmitter ID) [ 13.130514] pcieport 0000:00:00.0: device [17cb:0115] error status/mask=00001000/0000e000 [ 13.130516] pcieport 0000:00:00.0: [12] Timeout Fix this temporarly on SA8775P/Lemans platform by adding no_l0s = true to cfg_1_34_0 for SA8775P, so that PCI_EXP_LNKCAP_ASPM_L0S is cleared from the Root Port and ASPM L0s is prevented from being negotiated. Fixes: f5cd8a9 ("PCI: dwc: Remove MSI/MSIX capability for Root Port if iMSI-RX is used as MSI controller") Assisted-by: Claude:claude-4-6-sonnet Link: https://lore.kernel.org/all/20260419093934.1223027-1-shengchao.guo@oss.qualcomm.com/ Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
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Updated now as suggested. |
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Enabling MSI on the Root Port triggers frequent AER errors and, in some cases,
SMMU faults on RB4 and RB8 platforms. The PCIe controller does not reliably
support MSI when using the Synopsys MSI implementation, and disabling MSI on
the Root Port exposed these AER issues.
A proper fix is under discussion with the SVE team. Until then, disable PCIe
L0s on RB4 and RB8 as a temporary workaround to stabilize the link and unblock
WLAN functionality for the RC3 release.
This change is a platform-specific mitigation and should be reverted once a
correct fix is available.
CRs-Fixed: 4489177