Add Purwa camera support#502
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…pm8010 camera PMIC with voltage levels for IR and RGB camera" This reverts commit 7a52ef7. This patch is reverted because it is superseded by a newer revision. Subsequent Purwa changes are based on the updated version. Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
… sensor on CSIPHY4" This reverts commit 3020335. This patch is reverted because it is superseded by a newer revision. Subsequent Purwa changes are based on the updated version. Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
…PMIC with voltage levels for IR and RGB camera" This reverts commit e008c74. This patch is reverted because it is superseded by a newer revision. Subsequent Purwa changes are based on the updated version. Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
…sor on CSIPHY4" This reverts commit d892747. This patch is reverted because it is superseded by a newer revision. Subsequent Purwa changes are based on the updated version. Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
…,id=m regulators" This reverts commit f4615f9. This patch is reverted because it is superseded by a newer revision. Subsequent Purwa changes are based on the updated version. Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
…ion" This reverts commit bbbb1d9. This patch is reverted because it is superseded by a newer revision. Subsequent Purwa changes are based on the updated version. Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
This reverts commit bf65bd5. This patch is reverted because it is superseded by a newer revision. Subsequent Purwa changes are based on the updated version. Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
This reverts commit c4f6faf. This patch is reverted because it is superseded by a newer revision. Subsequent Purwa changes are based on the updated version. Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
…ion" This reverts commit 05d8e13. This patch is reverted because it is superseded by a newer revision. Subsequent Purwa changes are based on the updated version. Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
…om x1e" This reverts commit 100784f. This patch is reverted because it is superseded by a newer revision. Subsequent Purwa changes are based on the updated version. Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
This reverts commit f617c69. This patch is reverted because it is superseded by a newer revision. Subsequent Purwa changes are based on the updated version. Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
…nition structures" This reverts commit 9ee2b9b. This patch is reverted because it is superseded by a newer revision. Subsequent Purwa changes are based on the updated version. Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
…HY supplies to be optional" This reverts commit f82a866. This patch is reverted because it is superseded by a newer revision. Subsequent Purwa changes are based on the updated version. Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
… minItems: 5" This reverts commit 47343ac. This patch is reverted because it is superseded by a newer revision. Subsequent Purwa changes are based on the updated version. Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
…t for combo-mode endpoints" This reverts commit 33e6c2d. This patch is reverted because it is superseded by a newer revision. Subsequent Purwa changes are based on the updated version. Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
…al PHY handle definitions" This reverts commit 6240f0e. This patch is reverted because it is superseded by a newer revision. Subsequent Purwa changes are based on the updated version. Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
This reverts commit 84d8594. This patch is reverted because it is superseded by a newer revision. Subsequent Purwa changes are based on the updated version. Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
This reverts commit 1f7ef55. This patch is reverted because it is superseded by a newer revision. Subsequent Purwa changes are based on the updated version. Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
Add lane_positions to the DPHY configuration struct. This data-field represents the physical positions of the data-lanes indexed by lane number. Link: https://lore.kernel.org/all/20260325-dphy-params-extension-v1-1-c6df5599284a@linaro.org/ Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Pass an array of data-lane polarities from controller to PHY. A true value means the lane polarity is inverted. Link: https://lore.kernel.org/all/20260325-dphy-params-extension-v1-2-c6df5599284a@linaro.org/ Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
We need to identify which lane is the clock-lane as many different PHYs allow for a range of lanes, potentially any of the lanes to be the clock input lane on a PHY. Link: https://lore.kernel.org/all/20260325-dphy-params-extension-v1-3-c6df5599284a@linaro.org/ Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Specify the polarity of the clock lane in DPHY mode. When true this bool means the polarity is inverted. Link: https://lore.kernel.org/all/20260325-dphy-params-extension-v1-4-c6df5599284a@linaro.org/ Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Add a base schema initially compatible with x1e80100 to describe MIPI CSI2 PHY devices. The hardware can support both CPHY, DPHY and a special split-mode DPHY. We capture those modes as: - PHY_QCOM_CSI2_MODE_DPHY - PHY_QCOM_CSI2_MODE_CPHY - PHY_QCOM_CSI2_MODE_SPLIT_DPHY The CSIPHY devices have their own pinouts on the SoC as well as their own individual voltage rails. The need to model voltage rails on a per-PHY basis leads us to define CSIPHY devices as individual nodes. Two nice outcomes in terms of schema and DT arise from this change. 1. The ability to define on a per-PHY basis voltage rails. 2. The ability to require those voltage. We have had a complete bodge upstream for this where a single set of voltage rail for all CSIPHYs has been buried inside of CAMSS. Much like the I2C bus which is dedicated to Camera sensors - the CCI bus in CAMSS parlance, the CSIPHY devices should be individually modelled. Link: https://lore.kernel.org/all/20260326-x1e-csi2-phy-v5-1-0c0fc7f5c01b@linaro.org/ Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Add a new MIPI CSI2 driver in DPHY mode initially. The entire set of
existing CAMSS CSI PHY init sequences are imported in order to save time
and effort in later patches.
The following devices are supported in this drop:
"qcom,x1e80100-csi2-phy"
In-line with other PHY drivers the process node is included in the name.
Data-lane and clock lane positioning and polarity selection via newly
amended struct phy_configure_opts_mipi_dphy{} is supported.
The Qualcomm 3PH class of PHYs can do both DPHY and CPHY mode. For now only
DPHY is supported.
In porting some of the logic over from camss-csiphy*.c to here its also
possible to rationalise some of the code.
In particular use of regulator_bulk and clk_bulk as well as dropping the
seemingly useless and unused interrupt handler.
The PHY sequences and a lot of the logic that goes with them are well
proven in CAMSS and mature so the main thing to watch out for here is how
to get the right sequencing of regulators, clocks and register-writes.
The register init sequence table is imported verbatim from the existing
CAMSS csiphy driver. A follow-up series will rework the table to extract
the repetitive per-lane pattern into a loop.
Link: https://lore.kernel.org/all/20260326-x1e-csi2-phy-v5-2-0c0fc7f5c01b@linaro.org/
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
…andle definitions Add optional PHY handle definitions. This will allow for supporting both legacy PHY definitions as well as supporting the optional new handle based approach. Drop the legacy high-level 0p8 and 1p2 supplies as required, each PHY has its own individual rails. The old binding is still valid but with individual nodes we define the rails in the CSIPHY sub-nodes. Link: https://lore.kernel.org/all/20260326-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v11-1-5b93415be6dd@linaro.org/ Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
…mbo-mode endpoints Qualcomm CSI2 PHYs support a mode where two sensors may be attached to the one CSIPHY. When we have one endpoint we may have - DPHY 1, 2 or 4 data lanes + 1 clock lane - CPHY 3 wire data lane When we have two endpoints this indicates the special fixed combo-mode. - DPHY endpoint0 => 2+1 and endpoint1 => 1+1 data-lane/clock-lane combination. Link: https://lore.kernel.org/all/20260326-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v11-2-5b93415be6dd@linaro.org/ Reviewed-by: Christopher Obbard <christopher.obbard@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
…tructures Flag which SoCs have legacy - builtin PHY code. This will be useful in subsequent patches to inform PHY bringup logic if legacy bindings are available. Link: https://lore.kernel.org/all/20260326-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v11-5-5b93415be6dd@linaro.org/ Reviewed-by: Christopher Obbard <christopher.obbard@linaro.org> Tested-by: Christopher Obbard <christopher.obbard@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Add the ability to use a PHY pointer which interacts with the standard PHY API. In the first instance the code will try to use the new PHY interface. If no PHYs are present in the DT then the legacy method will be attempted. Link: https://lore.kernel.org/all/20260326-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v11-6-5b93415be6dd@linaro.org/ Reviewed-by: Christopher Obbard <christopher.obbard@linaro.org> Tested-by: Christopher Obbard <christopher.obbard@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
x1e is the first CAMSS SoC to use the new PHY interface. Drop the redundant legacy CSIPHY descriptions. Link: https://lore.kernel.org/all/20260326-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v11-7-5b93415be6dd@linaro.org/ Reviewed-by: Christopher Obbard <christopher.obbard@linaro.org> Tested-by: Christopher Obbard <christopher.obbard@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Introduce a new common Test Pattern Generator (TPG) implementation for Qualcomm CAMSS. This module provides a generic interface for pattern generation that can be reused by multiple platforms. Unlike CSID-integrated TPG, this TPG acts as a standalone block that emulates both CSIPHY and sensor behavior, enabling flexible test patterns without external hardware. Link: https://lore.kernel.org/all/20260317-camss_tpg-v10-1-b4cfa85c2e1b@oss.qualcomm.com/ Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> # Dell Inpsiron14p Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
TPG is connected to the csid as an entity, the link needs to be adapted. Link: https://lore.kernel.org/all/20260317-camss_tpg-v10-2-b4cfa85c2e1b@oss.qualcomm.com/ Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> # Dell Inpsiron14p Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
Add support for TPG found on LeMans, Monaco, Hamoa. Link: https://lore.kernel.org/all/20260317-camss_tpg-v10-3-b4cfa85c2e1b@oss.qualcomm.com/ Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> # Dell Inpsiron14p Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
Add bindings for the Camera Subsystem for X1P42100. The X1P42100 platform provides: - 2 x CSIPHY - 3 x TPG - 3 x CSID - 2 x CSID Lite - 1 x IFE - 2 x IFE Lite Link: https://lore.kernel.org/all/20260410-purwa_camss-v1-1-eedcf6d9d8ee@oss.qualcomm.com/ Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
The Purwa camera subsystem is a cut-down variant of the Hamoa CAMSS. Compared to Hamoa, Purwa provides only two CSIPHY instances and does not include the VFE1. Link: https://lore.kernel.org/all/20260410-purwa_camss-v1-2-eedcf6d9d8ee@oss.qualcomm.com/ Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
Add the CAMCC block for x1e80100. The x1e80100 CAMCC block is an iteration of previous CAMCC blocks with the exception of having two required power-domains not just one. Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260128-purwa-videocc-camcc-v1-6-b23de57df5ba@oss.qualcomm.com
Add in two CCI buses. One bus has two CCI bus master pinouts: cci_i2c_sda0 = gpio101 cci_i2c_scl0 = gpio102 cci_i2c_sda1 = gpio103 cci_i2c_scl1 = gpio104 The second bus has two CCI bus master pinouts: cci_i2c_sda2 = gpio105 cci_i2c_scl2 = gpio106 aon_cci_i2c_sda3 = gpio235 aon_cci_i2c_scl3 = gpio236 Link: https://lore.kernel.org/all/20260326-x1e-camss-csi2-phy-dtsi-v3-2-1d5a9306116a@linaro.org/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Add dtsi to describe the xe180100 CAMSS block 4 x CSIPHY 3 x TPG 2 x CSID 2 x CSID Lite 2 x IFE 2 x IFE Lite Link: https://lore.kernel.org/all/20260326-x1e-camss-csi2-phy-dtsi-v3-3-1d5a9306116a@linaro.org/ Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
…gulators Add pmic,id = m rpmh to regulator definitions. This regulator set provides vreg_l3m_1p8 the regulator for the ov08x40 RGB sensor on the CRD. Link: https://lore.kernel.org/all/20260326-x1e-camss-csi2-phy-dtsi-v3-4-1d5a9306116a@linaro.org/ Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
…SIPHY4 Define ov08x40 on cci1_i2c1. The RGB sensor appears on the AON CCI pins connected to CSIPHY4 in four lane mode. Link: https://lore.kernel.org/all/20260326-x1e-camss-csi2-phy-dtsi-v3-5-1d5a9306116a@linaro.org/ Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
…h voltage levels for IR and RGB camera Add the PM8010 PMIC providing the following voltage rails: vreg_l1m_r @ 1v2 IR sensor vreg_l2m_r @ 1v2 RGB sensor vreg_l3m_r @ 1v8 IR sensor vreg_l4m_r @ 1v8 RGB sensor vreg_l5m_r @ 2v8 IR sensor vreg_l7m_r @ 2v8 RGB sensor Link: https://lore.kernel.org/all/20260326-x1e-camss-csi2-phy-dtsi-v3-6-1d5a9306116a@linaro.org/ Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
…on CSIPHY4 Switch on the ov02c10 RGB sensor on CSIPHY4. Link: https://lore.kernel.org/all/20260326-x1e-camss-csi2-phy-dtsi-v3-7-1d5a9306116a@linaro.org/ Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
…amera PMIC with voltage levels for IR and RGB camera Add voltage regulators-8 for Camera on slim7x including: - vreg_l1m_1p2 - vreg_l3m_1p8 Link: https://lore.kernel.org/all/20260326-x1e-camss-csi2-phy-dtsi-v3-8-1d5a9306116a@linaro.org/ Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
…voltage regulator for RGB camera Some sleuthing work by Aleksandrs Vinarskis in the bowels of the ACPI tables for this part shows we need l7b_2p8 for the avdd supply. Link: https://lore.kernel.org/all/20260326-x1e-camss-csi2-phy-dtsi-v3-9-1d5a9306116a@linaro.org/ Suggested-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
…RGB sensor on CSIPHY4 Add in the RGB sensor on CSIPHY4. Link: https://lore.kernel.org/all/20260326-x1e-camss-csi2-phy-dtsi-v3-10-1d5a9306116a@linaro.org/ Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
…CAMSS RGB sensor Inspiron14 has a ov02e10 sensor on CSIPHY4. Enable the list of dependencies now. Link: https://lore.kernel.org/all/20260326-x1e-camss-csi2-phy-dtsi-v3-11-1d5a9306116a@linaro.org/ Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Add node for the X1P42100 camera subsystem. Link: https://lore.kernel.org/all/20260410-purwa_camss-v1-3-eedcf6d9d8ee@oss.qualcomm.com/ Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
enable camss node for purwa iot evk board camss tpg support. Link: https://lore.kernel.org/all/20260410-purwa_camss-v1-4-eedcf6d9d8ee@oss.qualcomm.com/ Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
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Looking at number of changes we are making here, please validate all targets, KLMTH |
Author
Have Tested with KLTHP, and all items have passed. |
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LGTM |
quic-tingweiz
approved these changes
Apr 27, 2026
Test Matrix
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CRs-Fixed: 4511688