Computer Engineering · NUST CEME · Rawalpindi, Pakistan
I don't just write code — I build the hardware it runs on.
# jawad.yaml
role : "CE Undergrad → targeting Google / NVIDIA"
focus : ["Computer Architecture", "RTL Design", "Embedded ML", "Cloud Systems"]
current : "3rd Year · 4th Semester"
languages : ["C++", "SystemVerilog", "Python", "Java", "PIC18 Assembly"]
tools : ["Vivado", "ESP-IDF", "Docker", "Azure", "TFLite", "CMake"]
boards : ["Basys-3 (Artix-7)", "ESP32-S3", "PIC18F452"]
competitive : "Codeforces: al_nusrati · Rating: B+"
building_next : "FPGA neural accelerator + quantum architecture exploration"Showing work that represents depth over breadth — hardware, systems, and AI at the intersection.
SystemVerilog · Vivado · Harvard Architecture
Full RV32I + RV32M 32-bit CPU designed from scratch. 5-stage pipeline IF → ID → EX → MEM → WB with inter-stage registers, a Forwarding Unit resolving RAW data hazards, and a Hazard Detection Unit for load-use stalls. Signed/unsigned arithmetic verified in GTKWave (−7 × 5 = −35, −7 × −1 = 7).
Verilog · SystemVerilog · Artix-7
Multi-system top-level design on a single Artix-7 fabric:
- OLED Pipeline — 96×64 real-time image renderer, 6144-pixel dual frame buffer via
$readmemh, SPI at 6.25 MHz - 8-bit ALU — demonstrates all three HDL abstraction levels in one module: gate-level structural (AND), dataflow (OR), behavioral procedural (XOR, ADD, SUB)
- Full-Alphabet 7-Seg — 62-character display driver, 200 Hz multiplexed refresh, 10 ms hardware debouncer
- 15+ additional systems: CipherX8, FSA, pipelined XOR, full adder, sequential counter — all synthesized and validated on-board
ESP32-S3 · ESP-IDF v5.5 · TensorFlow Lite · MobileNetV2
Bare-metal TinyML car with no Linux, no OS overhead. Trained MobileNetV2-0.35 steering-regression on the Udacity self-driving dataset (128×128 input, INT8 quantized, 599KB) and deployed directly on ESP32-S3-WROOM-1. Complete ESP-IDF firmware integrating OV3660 camera, LEDC motor PWM, MPU-6050 IMU, and HC-SR04 ultrasonic sensors. 40–60ms real-time inference latency via FreeRTOS.
C++ · Docker · Azure · Nginx · Flask
Distributed task scheduler with live deadlock avoidance. Implemented Banker's Algorithm with 4 concurrent worker threads and a dedicated deadlock-detector thread in C++. File-bridge IPC (state.json ↔ input.json) connects C++ backend to Flask/FastAPI dashboard. Containerised via Docker, reverse-proxied via Nginx, deployed on Azure RHEL VM (Standard D2s v3) with CMake build.
Azure · Docker · Ollama · Nginx
Self-hosted TinyLlama 1.1B on Azure via Ollama inside Docker, served publicly through Nginx as a clean REST API (/health, /api/generate). Debugged SELinux httpd_can_network_connect, firewalld rules, and Docker containerd storage overflow — remapped to 15 GB data disk via symlink.
Java 21 · JavaFX · Maven · jpackage · WiX
Professional-grade EDA tool with a decoupled MVC simulation engine performing real-time Boolean algebra independently of the UI. SVG-based schematic rendering via JavaFX SVGPath for infinitely scalable vector gates. Distributed as a 65MB self-contained Windows .exe with bundled JRE — built via Maven Shade + jpackage + WiX Toolset.
C++ · SFML · Custom DLL · ConsoleUtils
Custom templated Doubly Linked List for O(1) track navigation; domain layer holds a direct node<Track>* pointer, eliminating index traversal entirely. Integrated SFML Audio for real-time MP3 streaming. Shipped ConsoleUtils — an open-source C++ static library using ANSI escape codes for coloured interactive terminal UIs (now used independently).
Hardware & RTL ████████████████████░░ SystemVerilog · Verilog · FPGA · PCB Design
Computer Architecture ███████████████████░░░ Pipelines · Hazard Units · Memory Hierarchies
Embedded Systems ████████████████░░░░░░ ESP-IDF · FreeRTOS · PIC18 · Bare-Metal Firmware
Cloud & DevOps ██████████████░░░░░░░░ Azure · Docker · Nginx · CMake · Git
AI / ML on Edge █████████████░░░░░░░░░ TFLite · INT8 Quant · MobileNetV2 · Ollama
Systems Programming ████████████████████░░ C++ · Multithreading · IPC · DSA · OS Concepts
→ Exploring quantum computer architecture (gate models, error correction)
→ Building toward FPGA neural network acceleration
→ Deepening RISC-V pipeline design and memory system internals
→ Publishing technical content on LinkedIn: embedded AI · cloud · hardware
→ Competitive programming · Codeforces: al_nusrati